Computer systems and other electronic devices typically comprise integrated circuits, which may comprise semiconductors, transistors, wires, programmable logic devices, and programmable gate arrays, and which may be organized into chips, circuit boards, storage devices, and processors, among others.
The automated design of integrated circuits requires specification of a logic circuit by a designer. One technique for physically designing digital integrated logic circuits is known as the standard cell technique, in which physical layouts and timing behavior models are created for simple logic functions such as AND, OR, NOT, or FlipFlop. These physical layouts are known as “standard cells.” A large group of pre-designed standard cells is then assembled into a standard cell library, which is typically provided by a fabrication vendor who will eventually produce the actual chip that comprises the logic circuit. Examples of these standard cell libraries are available from fabrication vendors such as TSMC (Taiwan Semiconductor Manufacturing Company) or UMC (United Microelectronics Corporation). Automated tools available from companies such as Cadence Design Systems and Synopsys read a netlist description of the integrated circuit, or netlist representing the desired logical functionality for a chip (sometimes referred to as a behavioral or register-transfer-level description), and map it into an equivalent netlist composed of standard cells from the selected standard cell library. This process is commonly known as “synthesis.”
A netlist is a data structure representation of the electronic logic system that comprises a set of modules, each of which comprises a data structure that specifies subcomponents and their interconnection via wires, which are commonly called “nets.” The netlist describes the way in which standard cells and blocks are interconnected. Netlists are typically available in VERILOG, EDIF (Electronic Design Interchange Format), or VHDL (Very High Speed Integrated Circuit Hardware Design Language) formats.
Other tools available from companies such as Cadence or Synopsys read a netlist comprised of standard cells and create a physical layout of the chip by placing the cells relative to each other to minimize timing delays or wire lengths, then creating electrical connections (or routing) between the cells to physically complete the design of the desired circuit.
One important parameter that must be accounted for during the design of an integrated circuit is that of timing constraints. In particular, due to factors such as resistance, capacitance, and switching delays, signals that are propagated through an integrated circuit require some finite amount of time to reach various destinations. Further, often signals must reach their destinations within a certain time frame (typically before the end of a clock cycle). Otherwise, data would be missed due to its late arrival at a destination. Long interconnects tend to increase timing problems because the inherent resistance and capacitance of such long interconnects may delay the arrival of a signal at its destination beyond that which is acceptable.
One way to optimize timing is via buffer insertion into the circuit. In particular, the addition of one or more buffers into a relatively long interconnect in an integrated circuit design will typically improve the timing parameters for that interconnect, due to reduced load, reduced delay, and reduced slew, often without altering the overall length of an interconnect. Thus, by the selective addition of buffers to a design, a circuit design may be optimized to meet timing constraints.
A buffer is a special logic gate that is often manufactured to perform the same function as two inverters connected in series. An inverter is a single-input device that produces an output state opposite of the input state. Thus, if the input to the inverter is high, the output is low, and vice versa. A weak signal source (one that is not capable of sourcing or sinking very much current to a load) may be boosted by means of two inverters connected in series. By connecting the two inverters in series, the logic level of the output of the second inverter is unchanged from the logic level of the input of the first inverter in the series, but the signal is boosted or amplified. Locations at which buffers may be added are known as buffer bays.